Volume 8,Issue 9
Cross-Design Generalization of Lightweight Surrogate Models for Predicting Logic Synthesis Quality
The quality of results (QoR) of logic synthesis depends on the type and order of the optimization operators, and exhaustive evaluation is expensive, so machine-learning surrogates are widely used to predict recipe QoR. In the reference train and test lists released with the public dataset OpenABC-D, every design in the test list also appears in the training list, so figures reported on those lists need not reflect transfer to a new design. Using that dataset, this study takes 27 open-source circuits and 1,500 twenty-step ABC recipes, forming 40,500 labeled runs, trains four lightweight surrogates on 30 features, and scores them within each design under a random split and under leave-one-design-out (LODO). The median within-design mean absolute percentage error for area rises from 2.66% to 23.30% between the two protocols and falls back to 3.54% when the target is expressed relative to one reference-recipe calibration, although the coefficient of determination stays below zero. Under LODO, the median within-design rank correlation for area is 0.547, positive for 24 of the 27 held-out designs, so ranking information is partly transferable; for delay it is 0.007 (P=0.097) and no significant transfer is detected. Gradient boosting ranks best and trains in 0.161 seconds per fold. The evaluation protocol markedly changes apparent accuracy, and cross-design use of these features is supported for ranking area, not delay.
[1] Brayton R, Mishchenko A, 2010, ABC: An Academic Industrial-strength Verification Tool, in Computer Aided Verification, Lecture Notes in Computer Science. Springer, Berlin, 24–40. https://doi.org/10.1007/978-3-642-14295-6_5
[2] Yu C, Xiao H, De Micheli G, 2018, Developing Synthesis Flows without Human Knowledge. Proc. 55th Annual Design Automation Conference (DAC), 2018, 1–6. https://doi.org/10.1145/3195970.3196026
[3] Hosny A, Hashemi S, Shalan M, et al., DRiLLS: Deep Reinforcement Learning for Logic Synthesis. Proc. 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, 581–586. https://doi.org/10.1109/ASP-DAC47756.2020.9045559
[4] Wu N, Lee J, Xie Y, et al., 2022, LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. Proc. IEEE 33rd Int. Conf. Application-specific Systems, Architectures and Processors (ASAP), 11–18. https://doi.org/10.1109/ASAP54787.2022.00013
[5] Chowdhury AB, Tan B, Karri R, et al., 2021, OpenABC-D: A Large-Scale Dataset for Machine Learning Guided Integrated Circuit Synthesis. arXiv: 2110.11292. https://doi.org/10.48550/arXiv.2110.11292
[6] Neto WL, Li Y, Gaillardon PE, et al., 2023, FlowTune: End-to-end Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 42(6): 1912–1925. https://doi.org/10.1109/TCAD.2022.3213611
[7] Cui Z, Shen M, 2024, Automatic Multi-parameter Tuning for Logic Synthesis with Reinforcement Learning. Proc. 2nd Int. Symp. Electronics Design Automation (ISEDA), 318–323. https://doi.org/10.1109/ISEDA62518.2024.10617552
[8] Faez F, Karimi R, Zhang Y, et al., 2025, MTLSO: A Multi-task Learning Approach for Logic Synthesis Optimization. Proc. 30th Asia and South Pacific Design Automation Conference (ASP-DAC), 72–78. https://doi.org/10.1145/3658617.3697721
[9] Jiang W, Yan J, Sapatnekar SS, 2025, ML-based AIG Timing Prediction to Enhance Logic Optimization. Proc. Design, Automation and Test in Europe Conference (DATE), 1–2. https://doi.org/10.23919/DATE64628.2025.10993071
[10] Li F, Liu A, Liu S, et al., 2026, Bridging the Power Estimation Gap: A GNN-based Prediction Model for Approximate Logic Synthesis. Proc. Design, Automation and Test in Europe Conference (DATE), 1–7. https://doi.org/10.23919/DATE69613.2026.11539351
[11] Shi Z, Pan H, Khan S, et al., 2023, DeepGate2: Functionality-aware Circuit Representation Learning. Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1–9. https://doi.org/10.1109/ICCAD57390.2023.10323798
[12] Shi Z, Zheng Z, Khan S, et al., 2024, DeepGate3: Towards Scalable Circuit Representation Learning. Proc. 43rd IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1–9. https://doi.org/10.1145/3676536.3676791
[13] Liu J, Zhai J, Zhao M, et al., 2024, PolarGate: Breaking the Functionality Representation Bottleneck of And-inverter Graph Neural Network. Proc. 43rd IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1–9. https://doi.org/10.1145/3676536.3676834
[14] Ni L, Wang R, Liu M, et al., 2025, OpenLS-DGF: An Adaptive Open-source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(10): 3830–3843. https://doi.org/10.1109/TCAD.2025.3555506
[15] Chowdhury AB, Thakur S, Pearce H, et al., 2023, Invited Paper: Towards the Imagenets of ML4EDA. Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1–7. https://doi.org/10.1109/ICCAD57390.2023.10323663
[16] Chowdhury B, Tan B, Carey R, et al., 2023, Bulls-Eye: Active Few-shot Learning Guided Logic Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(8): 2580–2590. https://doi.org/10.1109/TCAD.2022.3226668
[17] Yang J, Chen K, Qiao J, et al., 2026, Hypergraph Pseudo-Label Learning with Neighborhood Consistency for Unseen Netlist Partitioning. Computer-Aided Design, 2026(199): 104115. https://doi.org/10.1016/j.cad.2026.104115
[18] Lu H, Fan S, Zhang S, et al., 2026, Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-Based Surrogate Model with Curriculum Learning. ACM Transactions on Design Automation of Electronic Systems, 31(4): 1–29. https://doi.org/10.1145/3768167
[19] Tseng IL, 2024, Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier Removal. Proc. IEEE Asia Pacific Conf. Circuits and Systems (APCCAS), 203–207. https://doi.org/10.1109/APCCAS62602.2024.10808773
[20] Won D, Kim T, 2025, EDA Tool Parameter Optimization through Fast and Reliable Machine-Learning Based Rank Prediction Model. Proc. ACM/IEEE 7th Symp. Machine Learning for CAD (MLCAD), 1–7. https://doi.org/10.1109/MLCAD65511.2025.11189232
